CPU caching understanding
up vote 4 down vote favorite 3 I tested the next code with Google Benchmark framework to measure memory access latency with different array sizes: int64_t MemoryAccessAllElements(const int64_t *data, size_t length) for (size_t id = 0; id < length; id++) volatile int64_t ignored = data[id]; return 0; int64_t MemoryAccessEvery4th(const int64_t *data, size_t length) for (size_t id = 0; id < length; id += 4) volatile int64_t ignored = data[id]; return 0; And I get next results (the results are averaged by google benchmark, for big arrays, there is about ~10 iterations and much more work performed for smaller one): There is a lot of different stuff happened on this picture and unfortunately, I can't explain all changes in the graph. I tested this code on single core CPU with next caches configuration: CPU Caches: L1 Data 32K (x1), 8 way associative L1 Instruction 32K (x1), 8 way associative L2 Unified 256K (x1), 8 way associative L3 Unified 30720K (x1), 20 ...